The Keysight M9193A DSR Pattern Editor with Data Converters combines the digital pattern editor1 with numerous data converters based on the Solstice-TDS In-converters from Test Systems Strategies Incorporated (TSSI). These TSSI In-converters make interfacing to digital design software easier.
- The WGL In-converter reads an ASCII file that’s compliant to the TSSI Waveform Generation Language (WGL) Specification.
- The STIL In-converter reads a text file that’s compliant to the standard STIL specification (IEEE Std 1450.0-1999). This In-converter is very useful for reading files produced by many ATPGs including Synopsys TetraMAX, Cadence Encounter, and Mentor Graphics FastScan.
- The Verilog In-converter converts a Value Change Dump (VCD) or an Extended Value Change Dump (EVCD) file generated by a Verilog simulator (e.g., Cadence IUS, Mentor Questa, or Synopsys VCS) into an event-based database. It is then cyclized by adding timing using supplied Cyclization tools.
- The ASCII In-converter is a flexible, tabular form reader. The TSSI ASCII format is a host-independent, human-readable representation of cyclized test patterns. This format is designed for importing a bulk of data as pre-ample or device specific setup patterns. The bulk data can be created from scratch or by converting from a different pattern format as long as it conforms to the TSSI ASCII format specification.
Once these test patterns are read into the system, they can then be edited and debugged using the pattern editor.
1 See the M9192A DSR Pattern Editor Software for a description of the pattern editor.
- Includes Graphical Pattern Editor
- WGL In-converter supports TSSI Waveform Generation Language
- Standard STIL In-converter supports ATPG files from Synopsys TetraMAX, Cadence Encounter, and Mentor Graphics FastScan
- Verilog In-converter for reading VCD/EVCD files
- Includes a complete set of Cyclization tools for adding timing (for Verilog files)
- ASCII In-converter allows simple text file input of patterns